Ron Gordon
Director – Power Systems
IBM announced and previewed the POWER9 technology at the annual Hot Chips meeting in California on August 23, 2016. This much-awaited announcement was well met and has been called a breakthrough in technology.
IBM announced 4 chips, differentiated by a 12 core 8x SMT and a 24 core 4x SMT, with memory controllers that support the Centaur buffer and a memory controller that supports direct attached memory. The 12 core P0WER9 process is slated for the Scale Up systems in 2018, and the 24 core processor is slated for the Scale Out and OpenPower systems beginning in the second half of 2017.
Some of the key items, in my opinion, are PCIe Gen4 with 48 lanes support, which will double the bandwidth of the adapters; integrated “BlueLink” (which is the NVlink now in the Power 822LC for HPC), improved performance on CAPI; DDR4 memory, and 2x to 4x the memory capacity per socket over POWER8 systems. Overall, IBM states that the expected throughput is 1.5 that of POWER8 systems.
Some of the cool stuff is: over 8 billion transistors, slightly larger die size, 17 metal layers, 7 TB/s on chip bandwidth, movement of data in/out of cores at 256 GB/s, new design of “slices” to optimize instruction execution speeds and SMT, L3 120 MB shared capacity NUCA cache, 512K L2 per SMT 8 core. This leads to big caches for massively parallel compute and heterogeneous interactions. WOW!
But we have to wait till next year to get one…
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